1. Field of the Invention
The present invention relates to a multilayer printed circuit board and a method for manufacturing the same, and more especially the multilayer printed circuit board such as a built-up printed circuit board and the method for manufacturing the same.
2. Description of the Related Art
Conventionally, an electronic device such as a computer device and communicating device generally includes a printed circuit board on which components such as SMDs (Surface Mount Devices) and through-hole mount devices are mounted.
In recent years, as electronic devices become highly functional, multilayer printed circuit boards are becoming more commonly used. For example, a built-up printed circuit board 101 serving as the multilayer printed board includes, as shown in FIG. 19, a core board 104, serving as a base, having a multilayer structure in which a plurality of conducting layers 102 and a plurality of insulating layers 103 are stacked and built-up layers 105 and 106 are formed on upper and lower sides of the core board 104.
Also, the built-up printed board 101 has core layer via holes (hereinafter, referred to as core layer vias) 109 passing through the plurality of conducting layers 102 and insulating layers 103 formed between the lower surface and upper surface of the core board 104, built-up layer via holes (hereinafter, referred to as built-up layer vias) 111a, 111b, and 111c also passing through the lower and upper surfaces of the built-up layers 105, and built-up layer vias 112a, 112b, and 112c passing through the lower and upper surfaces of the built-up layer 106, all of which are formed to establish connection between connecting terminals of the SMDs 107 each being an electronic device, and the conducting layers 102 serving as inner layers.
Each of the conducting layers 102 is made up of a signal layer, a power source layer, or a ground layer. Each of SMDs 107 is mounted on the built-up printed circuit board 101 in a state in which each corresponding connecting terminal is connected through solder to each of soldering pads 113 formed on a surface of each of the built-up layers 105 and 106.
In the built-up layers 105 and 106, a width (thickness) of each of the conducting layers and its interval (width of each of the insulating layers) can be made smaller until both the width and interval become about 15 μm. Moreover, a hole diameter of each of the built-up layer vias 111a, 111b, and 111c (112a, 112b, and 112c) used to establish connection among layers can be made smaller until the diameter becomes about 50 μm and, if the same signals are transmitted therethrough, a pitch among the built-up layer vias can be made smaller until the pitch becomes about 80 μm. This enables high density wiring.
On the other hand, in the core board 104, a width (thickness) of each of the conducting layers and its interval (width of an insulating layer) can be made smaller until both the width and interval become about 80 μm. Also, if the core board 104 is made up of 6 or more conducting layers stacked on one another, a hole diameter of each of the core layer vias 109 can be made smaller until the diameter becomes about 200 μm and its pitche can be made smaller until the pitch becomes about 700 μm.
Therefore, when the SDM 107 on an upper side (front side) is to be connected to the SDM 107 on a lower side (rear side) via each of the core layer vias 109, random pitches among the core layer vias 109 in the core board 104 are an obstacle to achieving high density wiring. Moreover, in the transmission of high-frequency signals in particular, since each of a signal line, power source line, or ground line is assigned at every pitch among the core layer vias 109, when a signal passes through each of the core layer vias 109, a distance of a path for a ground-return current is made long, as a result, causing high impedance.
In order to realize a reliable path for a ground return current of a signal passing through each of the core layer vias, technology is proposed in which each of the core layer vias is so configured as to have a coaxial structure made up of an inner via and outer via and the outer via is assigned to a ground line and inner via is assigned to a signal line (for example, Japanese Patent Application Laid-open Nos. 2001-244635, 2002-305377, and 2001-244636) and in which an outer layer of the coaxial structure is divided into two portions to use each of the portions as a signal line (for example, the above 2001-244636).
The above conventional technologies have a problem in that it is difficult to make a pitch among vias in the core layer sufficiently short. That is, in the above conventional technology, even if each of the core layer vias is so configured as to have a coaxial structure and the pitches among the vias are made short, the measure is not satisfactory enough to be contributable to high-density wiring. Also, even if an outer layer of the coaxial structure is divided into two portions, it is difficult to make the pitches sufficiently short and formation of the via of this type having the coaxial structure is not easy. Thus, both the suppression of high impedance during the transmission of high-frequency signals and the achievement of sufficiently short pitches among the vias in the conventional core layer are difficult.